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W191
Skew Controlled SDRAM Buffer
Features
* Six skew controlled CMOS outputs * Output skew between any two outputs is less than 150 ps * SMBus Serial configuration interface * 2.5 ns to 5 ns propagation delay * DC to 133 MHz operation (Commercial) * DC to 100 MHz operation (Industrial) * Single 3.3V supply voltage * Low power CMOS design packaged in a 16-pin SSOP (Small Shrink Outline Package)
Key Specifications
Supply Voltages: ...................................... VDDQ3 = 3.3V 5% Operating Temperature: (Commercial) ............. 0C to +70C Operating Temperature: (Industrial) .............. -40C to +85C Input Threshold:...................................................1.5V typical Maximum Input Voltage: .................................. VDDQ3 + 0.5V Input Frequency: (Commercial) ........................0 to 133 MHz Input Frequency: (Industrial).............................0 to 100 MHz BUF_IN to SDRAM0:5 Propagation Delay:.......2.5 ns to 5 ns Min. Output Edge Rate: ............................................. 1.0V/ns Max. Output Skew: ..................................................... 150 ps Output Duty Cycle:...................................45/55% worst case Output Impedance: ...................................................15 typ.
Block Diagram
Pin Configuration[1]
SDRAM0 GND
SDRAM0 SDRAM1 SDRAM2
SDATA SCLOCK
SMBus
Device Control
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDDQ3 SDRAM5 GND SDRAM4 VDDQ3 SDRAM3 GND SCLK
SDRAM1 BUF_IN GND SDRAM2 VDDQ3 SDATA
BUF_IN
SDRAM3 SDRAM4 SDRAM5
Note: 1. Internal pull-up resistor of 250K on SDATA and SCLK.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 9
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W191
Pin Definitions
Pin Name SDRAM0:5 Pin No. 1, 3, 6, 11, 13, 15 4 8 9 7, 12, 16 2, 5, 10, 14 Pin Type O Pin Description SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 2.5 to 5 ns. All outputs are skew controlled to within 150 ps of each other. Clock Input: This clock input has an input threshold voltage of 1.5V (typ). SMBus Data input: Data should be presented to this input as described in the SMBus section of this data sheet. Internal 250-k pull-up resistor. SMBus clock input: The SMBus Data clock should be presented to this input as described in the SMBus section of this data sheet. Internal 250-k pull-up resistor. Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane. Serial Control Serial control data is written to the W191 in ten bytes of eight bits each. Bytes are written in the order shown in Table 1 Writing Data Bytes Each bit in the data bytes control a particular device function. Bits are written MSB (most significant bit) first, which is bit 7. Table 1 gives the bit formats for registers located in Data Bytes 0-2.
BUF_IN SDATA SCLOCK VDDQ3 GND
I I/O I P G
Overview
The W191 is a skew controlled fanout buffer optimized for interface with registered DIMMs.
Functional Description
Output Drivers The W191 output buffers are CMOS type which deliver a rail-to-rail (GND to VDD) output voltage swing into a nominal capacitive load. Thus, output signaling is both TTL and CMOS level compatible. Nominal output buffer impedance is 15 . Table 1. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010
Byte Description Commands the W191 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W191 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W191, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W191, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal W191 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 2.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 2
Don't Care
Rev 1.0, November 20, 2006
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W191
Table 2. Data Bytes 0-2 Serial Configuration Map[2] Affected Pin Bit(s) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Pin No. 6 ----3 -1 -15 --13 ---11 -------Pin Name SDRAM2 ----SDRAM1 -SDRAM0 -SDRAM5 --SDRAM4 ---SDRAM3 -------Control Function Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable (Reserved) (Reserved) (Reserved) Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 0 Low ----Low ---Low --Low ---Low -------Data Byte 0 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable) Active ----Active ---Active --Active ---Active -------Bit Control 1
Data Byte 1 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
Data Byte 2 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
Note: 2. At power up all SDRAM outputs are enabled and active. Program Reserved bits to 0.
Rev 1.0, November 20, 2006
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W191
Absolute Maximum Ratings[3]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress Parameter VDDQ3, VIN TSTG TB TA TA Description Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature (Commercial) Operating Temperature (Industrial) rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to + 7.0 -65 to + 150 -55 to + 125 0 to + 70 -40 to + 85 Unit V C C C C
VDDQ3 = 3.3V 5% [4] Parameter IDD IDD
DC Electrical Characteristics: TA = 0C to +70C (Commercial), VDDQ3 = 3.3V 5%,TA = -40C to +85C (Industrial),
Description 3.3V Supply Current 3.3V Supply Current in three-state
Test Condition BUF_IN = 100 MHz BUF_IN = 100 MHz
Min.
Typ. 173 5
Max.
Unit mA mA
Logic Inputs (BUF_IN, OE, SCLOCK, SDATA) VIL VIH IILEAK IILEAK Input Low Voltage Input High Voltage Input Leakage Current, BUF_IN Input Leakage Current[5] GND-0.3 2.0 -5 -20 0.8 VDDQ3+0.5 +5 +5 V V A A
Logic Outputs (SDRAM0:5) VOL VOH IOL IOH Output Low Voltage Output High Voltage Output Low Current Output High Current IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V 3.1 65 70 100 110 160 185 50 mV V mA mA
Pin Capacitance/Inductance CIN COUT LIN Input Pin Capacitance (Except BUF_IN) Output Pin Capacitance Input Pin Inductance 5 6 7 pF pF nH
Notes: 3. Multiple supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. transmission lines with 20 pF capacitors. 4. Outputs loaded by 6" 60 5. OE, SCLOCK, and SDATA logic pins have a 250-k internal pull-up resistor (not CMOS level).
Rev 1.0, November 20, 2006
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W191
AC Electrical Characteristics: TA = 0C to +70C (Commercial), VDDQ3 = 3.3V 5%,TA = -40C to +85C (Industrial),
VDDQ3 = 3.3V 5% (Lump Capacitance Test Load = 30pF) Parameter fIN fIN tR tF tSR tSF tEN tDIS tPR tPF tD Zo Description Input Frequency (Commercial) Input Frequency (Industrial) Output Rise Edge Rate Output Fall Edge Rate Output Skew, Rising Edges Output Skew, Falling Edges Output Enable Time Output Disable Time Rising Edge Propagation Delay Falling Edge Propagation Delay Duty Cycle AC Output Impedance Measured at 1.5V 1.0 1.0 2.5 2.5 45 15 Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Test Condition Min. 0 0 1.0 1.0 Typ. Max. 133 100 4.0 4.0 150 150 8.0 8.0 5.0 5.0 55 Unit MHz MHz V/ns V/ns ps ps ns ns ns ns %
Rev 1.0, November 20, 2006
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W191
How To Use the Serial Data Interface
Electrical Requirements Figure 1 illustrates electrical characteristics for the serial interface bus used with the W191. Devices send data over the bus with an open drain logic output that can (a) pull the bus line low, or (b) let the bus default to logic 1. The pull-up resistor on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data. Although the W191 is a receive-only device (no data write-back capability), it does transmit an "acknowledge" data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance. pulse. A transitioning data line during a clock high pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). A write sequence is initiated by a "Start Bit" as shown in Figure 3. A "Stop Bit" signifies that a transmission has ended. As stated previously, the W191 sends an "acknowledge" pulse after receiving eight data bits in each byte as shown in Figure 4. Sending Data to the W191 The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition).
Signaling Requirements
As shown in Figure 2, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1)
VDD
VDD
~ 2k SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE
~ 2k
SDCLK CLOCK IN CLOCK OUT N DATA IN DATA OUT
SDATA CLOCK IN N
SCLOCK DATA IN DATA OUT
SDATA
N
CHIP SET (SERIAL BUS MASTER TRANSMITTER)
CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER)
Figure 1. Serial Interface Bus Electrical Characteristics .
Rev 1.0, November 20, 2006
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W191
TA
CK
Valid Data Bit
Change of Data Allowed
Figure 2. Serial Data Bus Valid Data Bit
A
K Start Bit Stop Bit
Figure 3. Serial Data Bus Start and Stop Bit
Rev 1.0, November 20, 2006
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W191
Signaling from System Core Logic Start Condition Slave Address (First Byte)
SDATA MSB 1 1 0 1 0 0 1 LSB 0 MSB
Stop Condition Command Code (Second Byte)
LSB
Byte Count (Third Byte)
MSB MSB
Last Data Byte (Last Byte)
LSB
SCLOCK
1
2
3
4
5
6
7
8
A
1
2
3
4
5
6
7
8
A
1
2
3
4
1
2
3
4
5
6
7
8
A
SDATA
Signaling by Clock Device
Acknowledgment Bit from Clock Device
Figure 4. Serial Data Bus Write Sequence
SDATA tSPF tLOW SCLOCK tSTHD tR tHIGH tF tDSU tDHD tSP tSPSU tSTHD tSPSU
Figure 5. Serial Data Bus Timing Diagrams
Ordering Information
Ordering Code W191HI W191H Package Type 16 pin = SSOP (150 mil) 16 pin = SSOP (150 mil) Temperature Range I = Industrial Commercial
Rev 1.0, November 20, 2006
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W191
Package Diagrams
Shrink Small Outline Package (SSOP 150 inch)
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 20, 2006
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